Lucien Breems (NXP Semiconductors)
Title: Wideband continuous-time ADCs for automotive applications
Abstract: Receivers used in automotive systems like terrestrial broadcast radio and radar-based ADAS depend on wideband analog-to-digital converters that deliver excellent linearity and high spectral purity. The continuous-time sigma-delta modulator fits the automotive receiver requirements very well, thanks to the inherent anti-alias filtering and high-gain feedback loop, but the maximum achievable bandwidth is limited by stability constraints. The continuous-time pipeline ADC architecture does not have this limitation, but its spurious performance depends on the (frequency dependent) matching accuracy between the analog and digital filters of the pipeline architecture. In this talk the latest cutting edge continuous-time sigma-delta and pipeline ADCs are presented that achieve better than 100dB SFDR in bandwidths up to several hundred MHz. The key architectural innovations, design challenges and calibration techniques are reviewed that enable this extreme performance.
Biography: Lucien Breems (Fellow, IEEE) received the M.Sc. and Ph.D. degrees in electrical engineering from Delft University of Technology in 1996 and 2001, respectively. From 2000 to 2006, he was with Philips Research and in 2007 he joined NXP Semiconductors. Since 2021, he has been a part-time Professor at Delft University of Technology. He is/has been a TPC member of the ISSCC, ASSCC, ESSCIRC, Symposium on VLSI Circuits, and ISLPED. He served as associate/guest editor for the IEEE JSSC, O-JSSCC and IEEE TCAS-II. He received the ISSCC Jan van Vessem paper award in 2001, 2011, and 2016; the RFIC Symposium industry best paper award in 2016; the ESSERC best paper award in 2024; and the IEEE Journal of Solid-State Circuits best paper award in 2011 and 2016. He was an IEEE Distinguished Lecturer from 2012 to 2013.
Pieter Harpe (Eindhoven University of Technology)
Title: High-Speed ADC Innovations: Architectures, Circuit Techniques & Calibration
Abstract: Applications such as communication continuously demand ADCs operating at higher speed (tens of GHz) while maintaining adequate energy efficiency. Making progress in this performance region is hampered by aperture limitations and auxiliary components like the input network and the clock drivers. Fortunately, technology scaling, hybrid ADC architectures, and advanced calibration methods have contributed to performance improvements. In this presentation, the main design challenges are reviewed, and recent state-of-the-art high-speed ADC examples are highlighted. The presentation will cover hybrid ADC architectures, innovative circuit techniques, calibration methods, and auxiliary circuits, all in the context of high-speed ADCs.
Biography: Pieter Harpe received the MSc and PhD degrees from the Eindhoven University of Technology, and then he worked for several years at imec on ultra low-power ADCs. In 2011, he joined Eindhoven University of Technology, where he is currently an Associate Professor and lead of the Resource Efficient Electronics Lab. His main activities are on low-power analog and mixed-signal circuits. Dr. Harpe is TPC member for ISSCC and A-SSCC, Associate Editor for TCAS-I, SSCS AdCom Member-at-Large and SSCS Distinguished Lecturer.
Micheal Flynn (University of Michigan, Michigan, USA)
Title: High-Performance Noise-Shaping SAR ADCs
Abstract: Noise-shaping successive‑approximation‑register (SAR) ADCs offer excellent energy and area efficiencies. Researchers have introduced several techniques to improve bandwidth and resolution. Interleaving combines noise-shaping ADCs in parallel to increase bandwidth. The cascaded noise-shaping SAR architecture cascades multiple noise-shaping stages to provide high resolution, with a modest increase in area and power. The higher order of the proposed architecture significantly enhances robustness and eliminates the need for PVT calibration. A Hybrid architecture adds a continuous-time frontend to provide many of the benefits of continuous‑time ΔΣ modulators, and VCO‑based front ends provide these advantages with a very small silicon footprint. Finally, incremental NS‑SAR brings the benefits of noise shaping to high‑resolution, Nyquist‑rate conversion.
Biography: Michael Flynn is the Fawwaz T Ulaby Collegiate Professor of Electrical and Computer Engineering at the University of Michigan. He received the Ph.D. degree from Carnegie Mellon University, Pittsburgh, PA, USA, and the B.E. and M.Eng.Sc from the National University of Ireland in Cork, Ireland. He is a Guggenheim Fellow and an IEEE Fellow Dr. Flynn received the 2024 Semiconductor Industry Association University Researcher Award. He received the Rackham Distinguished Graduate Mentoring Award in 2020 and the University of Michigan Faculty Achievement Award in 2016. Flynn is a former Editor-in-Chief of the IEEE Journal of Solid-State Circuits and a former sub-committee chair for data conversion at ISSCC.
Francesco Conzatti (Infineon Technologies, Austria)
Title: High Linearity Delta-Sigma Analog to Digital Converters: From Discrete Time to Continuous-Time Architectures
Abstract: Analog to Digital Converters (ADC) are key components in several applications, for instance sensor interfaces, communication systems, radar sensing, just to name a few. ADC non-linearity leads to degraded performance at system level, for instance higher Bit-Error-Rate (BER), degraded Error Vector Magnitude (EVM) or audible artifacts (audio). Delta-Sigma-Modulators (DSMs) are proven to achieve very demanding linearity requirements and several techniques have been published in the State-of-the-Art in order to address DSM non linearities and in particular to linearize the feedback Digital to Analog Converter (DAC), which is the key component to guarantee overall signal fidelity. Dynamic Element Matching (DEM) is effective as a background linearization technique, but leads to an increase of both current consumption and loop delay. Another popular approach is calibrating the DAC, which complicates the ADC system integration and is often proposed as an off-chip background solution. Single-Bit DAC designs reach outstanding linearities, but their application is usually limited to low-speed and low-bandwidth scenarios. Recent works on Inherently Linear ADCs tackle these issues and propose converter architectures that do not need neither calibration nor DEM, but still can reach very competitive performance in terms of linearity for both low-speed and high-speed scenarios. In this context, this work will cover recent advancements on inherently linear Delta-Sigma ADCs, ranging from Discrete-Time (DT) to Continuous-Time (CT) architectures.
Biography: Francesco Conzatti received the Master degree in electronic engineering from the University of Udine, Italy, in 2008 and the Ph.D. from the University of Udine and from the Institut National Polytechnique, Grenoble, France, in 2012 . From 2012 to 2018 he was with Intel Austria where he has been involved in the design of Continuous-Time Delta Sigma modulators for Intel’s wireless products. In 2018 he joined Infineon Technologies Austria, Villach, as Lead Principal Engineer for analog and mixed signal design, mainly focusing on data converters for several sensor and automotive products.
John G. Kauffman (University of Ulm, Germany)
Title: Advances in high-resolution Incremental ADCs
Abstract: High-resolution, high-efficiency A/D converters are dominated by noise-shaping and oversampling architectures. However, in applications where true Nyquist-rate conversion is required, such as single-shot conversion, multiplexing, or time-interleaving, neither oversampling nor noise-shaping can be used. This is due to the very concepts that allow them to combine efficiency with performance, introduce memory into the system, and thus prevent sample-to-sample operation. This talk focusses on incremental delta-sigma ADCs as a solution to this. It combines Nyquist-rate conversion with high power efficiency. The theoretical background and state of the art (SoA) prototypes using dynamic reconfiguration techniques to reduce the impact of non-idealities on incremental A/D converters are reviewed. In particular, integrator slicing, variable bit-width (VBW), and recuperation phase (RP) are investigated based on several SoA implementations.
Biography: John G. Kauffman received the B.Sc. and M.Sc. degrees from Worcester Polytechnic Institute, Worcester, MA, USA, in 2004 and 2005, respectively, and the Ph.D. degree from the University of Ulm, Ulm, Germany, in 2013.,From 2005 to 2008, he was with the MEMS Division, Analog Devices, Wilmington, MA, USA. From 2008 to 2009, he was with the dc/dc Design Group, Linear Technology, Munich, Germany. From 2013 to 2017, he was with Intel GmbH, Munich, as an Intel Member of Technical Staff designing receiver ADC’s for Intel’s LTE products. While at Intel, he designed three different multimode CT delta-sigma ADCs and received five U.S.-granted patents. From 2017 to 2019, he was with Nokia Networks, Silicon Valley, CA, USA, as the Technical Leader for TX DAC design and later became the Research and Development Manager for 5G RFIC design delivering a 4T4R Sub 6-GHz transceiver for in-house platforms. Since 2019, he has been with the University of Ulm as the Group Leader furthering research in ADCs, DACs, and other mixed-signal architectures for high-speed and precision designs.
Drew Hall (UC San Diego, USA)
Title: Pseudo-Virtual-Ground Feedforward for Linear, High-Order VCO-Only ΔΣ ADCs
Abstract: Time-domain ΔΣ ADCs that use VCOs as integrators scale cleanly in advanced CMOS, but their largely open-loop nature makes it hard to achieve both high linearity and higher-order noise shaping. This talk introduces pseudo-virtual-ground feedforward (PVG-FF), a technique that feedforwards the PVG residue to suppress VCO nonlinearity while enabling higher-order noise shaping with only a single feedback DAC. The result is a power-efficient ADC architecture with wide dynamic range and large input swing. A measured prototype achieves 92.1 dB SNDR over a 2.5 kHz bandwidth, 123 dB peak SFDR, and 1.8 Vpp differential input range, with verified robustness across supply and temperature.
Biography: Dr. Drew A. Hall earned a B.S. in Computer Engineering (honors) from UNLV in 2005 and M.S./Ph.D. degrees in Electrical Engineering from Stanford in 2008 and 2012. He held internships at GE, Bently Nevada, and National Semiconductor, focused on low-power precision analog design, and was a research scientist at Intel Labs from 2011–2013 in the Integrated Biosensors Laboratory. Since 2013, he has been on the faculty at UC San Diego’s Jacobs School of Engineering, where he is a Professor of Electrical and Computer Engineering and an affiliate Professor of Bioengineering. His group develops CMOS bioelectronics and biosensor interfaces for medical and life-science applications. He has received multiple awards, including an NSF CAREER Award and an NIH Trailblazer Award.